We will check out and compile the Golden Hardware Reference Design (GHRD) and compile it. We start by cloning the git repository.

$  git clone https://github.com/arrow-socfpga/arrow-sockit-ghrd.git
Cloning into 'arrow-sockit-ghrd'...
remote: Enumerating objects: 8, done.
remote: Counting objects: 100% (8/8), done.
remote: Compressing objects: 100% (8/8), done.
remote: Total 697 (delta 1), reused 4 (delta 0), pack-reused 689
Receiving objects: 100% (697/697), 15.21 MiB | 2.63 MiB/s, done.
Resolving deltas: 100% (441/441), done.
$  cd arrow-sockit-ghrd

Then we list the branches to find the revision that closest match our version or Quartus.

git branch -a
* master
  remotes/origin/HEAD -> origin/master
  remotes/origin/master
  remotes/origin/sockit-ghrd-1080p-16.1
  remotes/origin/sockit-ghrd-16.1
  remotes/origin/sockit-ghrd-19.1

The closest match we can see is for Quartus version 19.1, so we check out that branch and make our own branch to play.

$  git checkout sockit-ghrd-19.1
Branch 'sockit-ghrd-19.1' set up to track remote branch 'sockit-ghrd-19.1' from 'origin'.
Switched to a new branch 'sockit-ghrd-19.1'
$  git branch play_20.1
$  git checkout play_20.1
Switched to branch 'play_20.1'

We set up the environment using the aliases we created earlier and have a look.

$  quartus20.1
------------------------------------------------
Altera Nios2 Command Shell

Version 20.1, Build 711
------------------------------------------------
$  make
*****************************************
*                                       *
* Manage QuartusII/QSys design          *
*                                       *
*     Copyright (c) 2015                *
*     All Rights Reserved               *
*                                       *
*****************************************

*********************
* Target: help
*   Displays this info (i.e. the available targets)
*********************
* Target: preloader
*   Build Preloader BSP for this design into software/preloader directory
*********************
* Target: program_fpga
*   Quartus program sof to your attached dev board
*********************
* Target: program_qspi
*   Flash program preloader into QSPI Flash
*********************
* Target: qsys_edit
*   Launch QSys GUI
*********************
* Target: quartus_edit
*   Launch Quartus II GUI
*********************
* Target: scrub_clean
*   Restore design to its barebones state
*********************
* Target: sof
*   QSys generate & Quartus compile this design
*********************
* Target: tgz
*   Create a tarball with the barebones source files that comprise this design
*********************
* Target: uboot
*   Build U-Boot into software/preloader directory
*********************

We open the GUI.

$  make quartus_edit

From the GUI we launch the IP Upgrade Tool and perform an automatic upgrade. We wait for the upgrade to finish and close the dialog and the Quartus main window. Now it is time to have a look at the the system in the Platform Designer.

$  make qsys_edit

It fails to open due to the following error.

Error: The system could not be opened: /home/oddbjorn/arrow-sockit-ghrd/sockit_ghrd.BAK.qsys.  "sockit_ghrd.BAK" is not a valid HDL name.

So we remove the backup file and try again.

$  rm sockit_ghrd.BAK.qsys
$  make qsys_edit

This time it opens the correct file and we can have a look at the system. We see that the HPS is included. We see a few JTAG to Avalon Master Bridge. There is one to access the slaves in the HPS through the FPGA-to-HPS bridge (f2h) called hps_only_master. There is one called fpga_only_master connected to the slaves on the FPGA. The last is called f2sdram_only_master which is connected to the FPGA-to-HPS SDRAM Interface (f2h_sdram) in order to access the SDRAM connected to the HPS. The HPS-to-FPGA (h2f) bridge is connected to all the slaves in the FPGA through a pipeline bridge. We will play with these bridges between the FPGA and the HPS in a later post. We see that we have a JTAG UART for debug. We will also be playing with the JTAG and the JTAG to Avalon Master Bridges in a later post. We also see that there are Parallel I/O (PIO) connected to the buttons, dip switches and the LEDs. We use Make to build the FPGA bitstream, also called sof (SRAM Object File).

$  make sof

Time to read reddit.com/r/FPGA while we wait for it to build. When it has completed we can load the sof file to the FPGA using the JTAG.

$  make program_fpga
jtagconfig
1) CV SoCKit [3-1.3]
  02D020DD   5CSEBA6(.|ES)/5CSEMA6/..
  4BA00477   SOCVHPS

quartus_pgm --mode=jtag  --operation=p\;output_files/sockit_ghrd.sof"@1"
Info: *******************************************************************
Info: Running Quartus Prime Programmer
    Info: Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
    Info: Copyright (C) 2020  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions
    Info: and other software and tools, and any partner logic
    Info: functions, and any output files from any of the foregoing
    Info: (including device programming or simulation files), and any
    Info: associated documentation or information are expressly subject
    Info: to the terms and conditions of the Intel Program License
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details, at
    Info: https://fpgasoftware.intel.com/eula.
    Info: Processing started: Tue Sep 29 21:02:51 2020
Info: Command: quartus_pgm --mode=jtag --operation=p;output_files/sockit_ghrd.sof@1
Info (213045): Using programming cable "CV SoCKit [3-1.3]"
Info (213011): Using programming file output_files/sockit_ghrd.sof with checksum 0x02BA2921 for device 5CSXFC6D6F31@1
Info (209060): Started Programmer operation at Tue Sep 29 21:02:52 2020
Info (209016): Configuring device index 1
Info (209017): Device 1 contains JTAG ID code 0x02D020DD
Info (209007): Configuration succeeded -- 1 device(s) configured
Info (209011): Successfully performed operation(s)
Info (209061): Ended Programmer operation at Tue Sep 29 21:02:55 2020
Info: Quartus Prime Programmer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 332 megabytes
    Info: Processing ended: Tue Sep 29 21:02:55 2020
    Info: Elapsed time: 00:00:04
    Info: Total CPU time (on all processors): 00:00:01
jtagconfig  -n
1) CV SoCKit [3-1.3]
  02D020DD   5CSEBA6(.|ES)/5CSEMA6/..
    Design hash    853A2238C890EFA5FB91
    + Node 0C206E00  JTAG PHY #0
    + Node 0C206E01  JTAG PHY #1
    + Node 0C206E02  JTAG PHY #2
    + Node 00486E00  Source/Probe #0
    + Node 0C006E00  JTAG UART #0
    + Node 30006E00  Signal Tap #0
  4BA00477   SOCVHPS

The FPGA is now programmed, but it offers no visual prof of success so let us open system-console to see if we can toggle some LEDs.

$  system-console --project_dir=. --cli

Lets start by listing the JTAG masters.

% get_service_paths master
{/devices/5CSEBA6(.|ES)|5CSEMA6|..@1#3-1.3#CV SoCKit/(link)/JTAG/alt_sld_fab_sldfabric.node_0/phy_0/f2sdram_only_master.master} {/devices/5CSEBA6(.|ES)|5CSEMA6|..@1#3-1.3#CV SoCKit/(link)/JTAG/alt_sld_fab_sldfabric.node_1/phy_1/fpga_only_master.master} {/devices/5CSEBA6(.|ES)|5CSEMA6|..@1#3-1.3#CV SoCKit/(link)/JTAG/alt_sld_fab_sldfabric.node_2/phy_2/hps_only_master.master}

We see the three same masters as we saw in Platform Designer. We want to open the fpga_only_master to access the LEDs, buttons and switches. It is listed as the second master.

% set fom [ lindex [ get_service_paths master ] 1 ]
/devices/5CSEBA6(.|ES)|5CSEMA6|..@1#3-1.3#CV SoCKit/(link)/JTAG/alt_sld_fab_sldfabric.node_1/phy_1/fpga_only_master.master
% open_service master $fom

With the opened master lets write to the address of led_pio to toggle the FPGA LEDs. The address, 0x00010040, can be found in Platform Designer.

% master_write_8 $fom 0x00010040 0xA
% master_write_8 $fom 0x00010040 0x5

You should now see the FPGA LEDs toggling.

In order to access devices in the HPS we first need to start the HPS and enable the bridges. If we try to do it now the access will hang, so that will have to wait until a later post.